1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices in which the stability of the negative voltage generated by a negative voltage generating circuit is increased, and methods of manufacturing such semiconductor integrated circuit devices.
2. Description of the Related Art
As manufacturing processes have become progressively miniaturized in recent years, there has arisen a need for system LSIs for specific applications that include dynamic random access memories (hereinafter, abbreviated as DRAM) and for which standard CMOS manufacturing processes can be used.
Conventionally, the negative voltage (VBB voltage) generated by a negative voltage generating circuit in the DRAM has been used as the well voltage of memory cell portions employing a triple well structure. Planar memory cell structures have been adopted as a way to form DRAMs through standard CMOS processing, as mentioned above, without the use of a triple well.
Here, FIG. 11 shows a planar memory cell structure. Numeral 300 denotes a p-type semiconductor substrate connected to a ground voltage VSS. An n-well 310 is formed in the upper portion of the p-type semiconductor substrate 300, and in the upper portion of the n-well 310 are formed a high-concentration n-type diffusion layer 320 and high-concentration p-type diffusion layers 330. A VDD power source is connected via the high-concentration n-type diffusion layer 320, and a bit line BL is connected to one of the high-concentration p-type diffusion layers 330. A gate 340 is a word line WL with an internally stepped down power source VINT as its power source. The two high-concentration p-type diffusion layers 330 and the gate 340 together make up a PMOS access transistor 360. The high-concentration p-type diffusion layer 330 to which the bit line BL is not connected and a memory cell plate 350 connected to VBB make up a PMOS memory cell capacitor 370.
This memory cell operates as follows. The PMOS access transistor 360 is activated by setting the gate 340, that is, the word line WL, to the ground voltage VSS, and data are written by injecting a charge from the bit line BL into the channel region formed near the surface of the n-well 310 below the memory cell plate 350.
FIG. 12 is an equivalent circuit of this planar memory cell structure.
As shown in FIGS. 11 and 12, the VDD power source, which is a positive voltage, is used for the well voltage of the memory cell portion in which the PMOS access transistor 360 is employed, and the VBB voltage, which is a negative voltage, is used as the memory cell plate power source for the PMOS memory cell capacitor 370.
Next, a conventional semiconductor memory device with the above planar memory cell structure is described. FIG. 13 is a block diagram of the conventional semiconductor memory device. Numeral 410 denotes a VBB voltage generating circuit and 480 denotes a memory cell array having a memory cell plate with a negative charge. The VBB voltage generating circuit 410 includes a charge pump circuit 420 for generating VBB voltage, a ring oscillator 430 for generating pulse signals that cause the charge pump circuit 420 to perform a charge pump operation, a VBB voltage detection circuit 450 to which the VBB voltage is fed back and which generates signals (BBDOWN) for activating the ring oscillator 430, and a constant voltage generating circuit 460 for generating a reference voltage that is used by the VBB voltage detection circuit 450. The VBB voltage detection circuit 450 is made of a comparison voltage generating circuit 451 and a non-inverting amplifier 454 for lowering the VBB voltage.
The comparison voltage generating circuit 451 is a series circuit of a resistor R21 and a resistor R22. One terminal of the resistor R21 is connected to a node of a constant voltage VREG output from the constant voltage generating circuit 460, and the other end is connected to one terminal of the resistor 22 and is also connected to a node of a comparison voltage VCOMP that is applied to a non-inverting input terminal (+) of the non-inverting amplifier 454 for lowering the VBB voltage. The other end of the resistor R22 is connected to the VBB node.
The operation of the semiconductor memory device configured as above is described below. The non-inverting amplifier 454 has two input terminals and one output terminal. As mentioned above, the comparison voltage VCOMP is applied to the non-inverting input terminal (+) and a reference voltage VREF (in the present conventional example, the ground voltage VSS) is applied to the inverting input terminal (xe2x88x92). Consequently, if the VCOMP voltage is higher than the reference voltage VREF, that is, the ground voltage VSS, then a voltage of the BBDOWN node, which is the output, become a logic xe2x80x98HIGHxe2x80x99 voltage (hereinafter, referred to simply as HIGH voltage), and if the VCOMP voltage is lower than the ground voltage VSS, then the BBDOWN node becomes a logic xe2x80x98LOWxe2x80x99 voltage (hereinafter, referred to simply as LOW voltage).
When the BBDOWN voltage is HIGH voltage, the ring oscillator 430 self-oscillates, and the charge pump circuit 420 that receives this oscillated pulse executes a pumping operation that causes the VBB voltage to drop. On the other hand, when the BBDOWN voltage is LOW voltage, the ring oscillator 430 does not self-oscillate, and the operation of the charge pump circuit 420 is stopped.
The VCOMP voltage is determined by the voltage division ratio of the resistor R21 and the resistor R22, and is expressed by Equation (1).
VCOMP=VBB+{R22(VREGxe2x88x92VBB)}/(R21+R22)xe2x80x83xe2x80x83(1) 
If the resistor voltage division ratio determined by the resistor R21 and the resistor R22 is such that the VCOMP voltage is equal to the VREF (VSS) voltage when the VBB voltage is a desired voltage, the VBB voltage can be maintained at the desired voltage.
However, with the aforementioned conventional semiconductor memory device, although the VBB voltage can be actively lowered by activating the charge pump circuit, there is no function for raising the VBB voltage. Originally, if left free, the VBB voltage rises naturally due to leakage current, for example, in due time. Moreover, because the requirements for voltage control of the VBB current were not particularly stringent (for example, about xc2x150 mV fluctuation), it was adequate to provide only a function for lowering the VBB voltage.
As mentioned above, however, if the VBB voltage, which is a negative voltage, is used as the plate power source of the memory cell capacitor, then more stringent voltage control for the VBB voltage (for example, about xc2x110 mV fluctuation) becomes necessary. Also, ordinarily, due to reductions in power, the ability of the VBB voltage generating circuit to supply negative current is limited, that is, there is a high output impedance. Thus, when writing data to the memory cell capacitor, the memory cell plate voltage fluctuates due to capacitive coupling. If the VBB voltage rises due to this capacitive coupling, the VBB voltage can be lowered to the set voltage by operating the charge pump circuit. However, if VBB falls below the set voltage, it takes time for the VBB voltage to return to the set voltage, because the conventional VBB voltage generating circuits do not have a function for lowering the voltage. If data are read out from the memory when the VBB voltage is lower than the set voltage, the read voltage becomes low due to coupling, and this is problematic because it leads to the read out of erroneous data.
The above problem is not limited to semiconductor memory devices, and is common to general semiconductor integrated circuit devices having a configuration in which negative voltage (VBB voltage) generated by a negative voltage generating circuit is supplied.
Therefore, in light of the foregoing conventional problems, it is an object of the present invention to provide a semiconductor integrated circuit device onto which is installed a circuit for raising the VBB voltage so as to raise the VBB voltage quickly and control the VBB voltage at high speeds, thereby achieving voltage stability and preventing malfunctions.
To solve the foregoing problems, a semiconductor integrated circuit device of the present invention is provided with a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal.
With this configuration, when the negative voltage falls below the second detection voltage, the voltage detection circuit generates a second detection signal, and in response to this second detection signal, the negative voltage raising circuit supplies current to the negative voltage node and thereby raises the voltage. Consequently, the function for raising the negative voltage is activated when the negative voltage is lower than the second detection voltage. By performing this control to raise the negative voltage quickly, a more stable negative voltage can be supplied to the load and malfunction of the semiconductor integrated circuit device can be prevented.
The second detection voltage may be lower than the first detection voltage.
The voltage detection circuit may have a configuration that includes a first comparison voltage generating circuit for outputting a first comparison voltage and a second comparison voltage in response to the voltage of the negative voltage node, a reference voltage generating circuit for outputting a reference voltage, a first amplifier for comparing the reference voltage and the first comparison voltage and amplifying the voltage difference between them to generate the first detection signal, and a second amplifier for comparing the reference voltage and the second comparison voltage and amplifying the voltage difference between them to generate the second detection signal.
The first comparison voltage generating circuit may have a configuration that includes a first resistive element, a second resistive element and a third resistive element, wherein one terminal of the first resistive element is connected to a constant voltage node, another terminal of the first resistive element is connected to one terminal of the second resistive element, another terminal of the second resistive element is connected to one terminal of the third resistive element, and another terminal of the third resistive element is connected to the negative voltage node. The second comparison voltage is the voltage of a node at which the first resistive element and the second resistive element are connected, and the first comparison voltage is the voltage of a node at which the second resistive element and the third resistive element are connected.
The reference voltage generating circuit may have a configuration that includes a fourth resistive element and a fifth resistive element, wherein one terminal of the fourth resistive element is connected to a constant voltage node, another terminal of the fourth resistive element is connected to one terminal of the fifth resistive element, and another terminal of the fifth resistive element is connected to a ground voltage. The reference voltage is the voltage of a node at which the fourth resistive element and the fifth resistive element are connected.
It is preferable that the fourth resistive element and the fifth resistive element have variable resistances, and that by changing the resistances of the fourth resistive element and the fifth resistive element, the voltage value of the reference voltage that is output from the reference voltage generating circuit can be changed.
Also, it is preferable that the first resistive element, the second resistive element, and the third resistive element have variable resistances, and that by changing the resistances of the first resistive element, the second resistive element, and the third resistive element, the voltage values of the first comparison voltage and the second comparison voltage that are output from the comparison voltage generating circuit can be changed.
It is preferable that each of the fourth resistive element and the fifth resistive element includes a plurality of resistors connected in series, a fuse is connected in parallel to at least one of the resistors, and the overall resistance can be changed by opening at least one of the fuses.
Also, it is preferable that each of the first, second, and the third resistive elements includes a plurality of resistors connected in series, a fuse is connected in parallel to at least one of the resistors, and the overall resistance can be changed by opening at least one of the fuses.
The reference voltage generating circuit may have a configuration that includes a fourth resistive element and a fifth resistive element, wherein one terminal of the fourth resistive element is connected to a constant voltage node, another terminal of the fourth resistive element is connected to one terminal of the fifth resistive element, and another terminal of the fifth resistive element is connected to a ground voltage, the reference voltage being the voltage of a node at which the fourth resistive element and the fifth resistive element are connected. At least one of the first, second, third, fourth, and fifth resistive elements includes a plurality of resistors connected in series, a fuse is connected in parallel to at least one of the resistors, and the overall resistance can be changed by opening at least one of the fuses.
It is preferable that the resistances of the plurality of resistors are set so that the negative voltage is changed linearly by trimming the fuse.
The negative voltage raising circuit may be a transistor having a control terminal for receiving the second detection signal, a terminal connected to a positive voltage power source, and a terminal connected to the negative voltage node. Alternatively, the negative voltage raising circuit may be a transistor having a control terminal for receiving the second detection signal, a terminal that is grounded, and a terminal connected to the negative voltage node.
The first amplifier and the second amplifier may have respective first and second current mirror-type differential amplifiers, and a constant current value of the transistor serving as a constant current source of the second current mirror-type differential amplifier is larger than a constant current value of the transistor serving as a constant current source of the first current mirror-type differential amplifier. Alternatively, each of the first amplifier and the second amplifier may have a three-stage current mirror-type differential amplifier.
The first comparison voltage may be lower than the second comparison voltage. It is preferable that the number of transistors making up the negative voltage raising circuit can be changed corresponding to the size of a load that is connected to the negative voltage node.
It is preferable that the device further includes a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load. In this configuration, a memory cell array further may be included, and that the load may be a memory cell plate of the memory cell array. Additionally, it is preferable that the size of the load can be changed depending on the number of installed memory bits, and that the number of transistors making up the negative voltage raising circuit may be changed in response to the number of installed memory bits. Also, it is preferable that the size of the load can be changed depending on the number of activated blocks of the memory cell array, and the number of transistors making up the negative voltage raising circuit can be changed in response to the number of activated blocks.
It is preferable that the device further includes a diode, one terminal of which is connected to a node connecting the resistor and the load, and that another end of the diode is connected to the ground voltage.
It is preferable that the device further includes a pad connected to a node connecting the resistor and the load, and that via the pad, voltage can be imparted from the outside and a voltage of the node can be detected. Also, it is possible that an output node of the negative voltage raising circuit is connected to a node connecting the resistor and the load, and that an output node of the negative voltage raising circuit is connected to the negative voltage node via the resistor.
The device further may include a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load. Further the first comparison voltage generating circuit may include a second comparison voltage generating circuit and a third comparison voltage generating circuit. The second comparison voltage generating circuit may have a sixth resistive element and a seventh resistive element, one terminal of the sixth resistive element being connected to a constant voltage node, another terminal of the sixth resistive element being connected to one terminal of the seventh resistive element, and another terminal of the seventh resistive element being connected to the negative voltage node. The third comparison voltage generating circuit may have an eighth resistive element and a ninth resistive element, one terminal of the eighth resistive element being connected to the constant voltage node, another terminal of the eighth resistive element being connected to one terminal of the ninth resistive element, and another terminal of the ninth resistive element being connected to a node linking the resistor and the load. The first comparison voltage is the voltage of a node at which the sixth resistive element and the seventh resistive element are connected, and the second comparison voltage is the voltage of a node at which the eighth resistive element and the ninth resistive element are connected.
In this configuration, it is preferable that each of the eighth resistive element and the ninth resistive element have variable resistances, and that by changing the resistances of the eighth resistive element and the ninth resistive element, the voltage value of the second comparison voltage that is output from the comparison voltage generating circuit can be changed. Also, it is preferable that one of the sixth resistive element and the seventh resistive element have variable resistances, and that by changing the resistances of the sixth resistive element and the seventh resistive element, the voltage value of the first comparison voltage that is output from the comparison voltage generating circuit can be changed.
It is preferable that a difference between a set voltage of the first detection voltage and a set voltage of a second detection voltage is larger than a maximum value of the total of an offset voltage of the first amplifier and an offset voltage of the second amplifier. Also it is also preferable that a capacitor is inserted between a reference voltage node to which the output of the reference voltage generating circuit is supplied and a ground voltage.
A method of manufacturing a semiconductor integrated circuit of the present invention is a method of manufacturing a semiconductor integrated circuit device with which the voltage value of the reference voltage that is output from the reference voltage generating circuit can be changed by adjusting the resistances of the aforementioned fourth resistive element and the fifth resistive element.
The method includes: preparing a semiconductor integrated circuit device including, in addition to the above configuration, a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load, and a pad that is connected to a node connecting the resistor and the load, wherein a voltage of the negative voltage node can be detected via the pad; and detecting, during wafer testing, a voltage appearing on the pad and changing the resistances of the fourth resistive element and the fifth resistive element so as to adjust the voltage value of the reference voltage that is output from the reference voltage generating circuit.
The aforementioned semiconductor integrated circuit device with which the voltage value of the first comparison voltage and the second comparison voltage that are output from the comparison voltage generating circuit can be changed by adjusting the resistances of the first resistive element, the second resistive element and the third resistive element, can be manufactured through the following method.
The method includes; preparing a semiconductor integrated circuit device including, in addition to the above configuration, a resistor, one terminal of which is connected to the negative voltage node and another terminal of which is connected to a load, and a pad that is connected to a node connecting the resistor and the load, wherein a voltage of the negative voltage node can be detected via the pad; and detecting, during wafer testing, a voltage appearing on the pad and changing the resistances of the first resistive element, the second resistive element, and the third resistive element so as to adjust the voltage values of the first comparison voltage and the second comparison voltage that are output from the comparison voltage generating circuit.
Another semiconductor integrated circuit device of the present invention is provided with a charge pump circuit for outputting a predetermined output voltage to an output voltage node; a voltage detection circuit for generating a first detection signal when the voltage of the output voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the output voltage node has reached a second detection voltage; an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit; and an output voltage transition circuit that has an output terminal connected to the output voltage node, and that is driven in response to the second detection signal so as to change the voltage of the output voltage node through the output of the output terminal to a direction reverse to a direction driven by the charge pump circuit.
According to this configuration, when the output voltage of the charge pump circuit reaches the second detection voltage, the voltage detection circuit generates a second detection signal, and in response to the second detection signal, the output voltage transition circuit changes the direction of the voltage of the output voltage node to opposite the direction in which it is driven by the charge pump circuit. Thus, by performing a control in which the voltage is rapidly shifted to the opposite direction even if the output voltage of the charge pump circuit exceeds the desired value, a more stable output voltage can be supplied to the load and malfunction of the semiconductor integrated circuit device can be prevented.